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october 2012 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 ft8010 ? reset timer with configurable delay time ft8010 reset timer with configurable delay time features ? long delay configurable to 7.5 or 11.25 seconds ? primary and secondary input reset pins ? push-pull and open-drain output pins ? 1.8 v to 5.0 v operation (t a =-40c to +85c) ? 1.7 v to 5.0 v operation (t a =-25c to +85c) ? 1.65 v to 5.0 v operation (t a =0c to +85c) ? packaged in 10-lead umlp (1.4 mm x 1.8 mm) and 8-lead mlp (2.0 mm x 2.0 mm) packages description the ft8010 is a timer for resetting a mobile device where long reset times are needed. the long time delay helps avoid unintended resets caused by accidental key presses. two delays can be selected by hard-wiring the dsr pin: 7.5 20% seconds or 11.25 20% seconds. the ft8010 has two identical inputs for single or dual switch resetting capability. the device has two outputs: a push-pull output with 0.5 ma drive and an open-drain output with 0.5 ma pull-down drive. ft8010 draws minimal i cc current when inactive and functions over a wide 1.65 v to 5.0 v power supply range. ordering information part number operating temperature range package packing method ft8010umx -40 ? c to +85 ? c 10-lead, ultrathin mlp, 1.4 x 1.8 x 0.55 mm package, 0.40 mm pitch 5000 units tape and reel FT8010MPX -40 ? c to +85 ? c 8-lead, mlp 2.0 x 2.0 x 0.8 mm package, 0.5 mm pitch 3000 units tape and reel
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 2 ft8010 ? reset timer with configurable delay time block diagram figure 1. block diagram
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 3 ft8010 ? reset timer with configurable delay time pin configuration figure 2. mlp pin configuration ( 1 ) (top through view) figure 3. umlp pin configuration ( 2 ) (top through view) note: 1. the dap may be a no connect or it may be tied to ground. 2. nc = no connect pin definitions mlp pin # umlp pin # name description 1 10 rst2 push-pull output, active high 2 1 gnd ground 3 2 /sr1 secondary reset input, active low 4 3 /rst1 open-drain output, active low 5 5 dsr delay selection input (must be tied directly to gnd or v cc ; do not use pull-up or pull-down resistors.) 6 6 trig test pin, tied to gnd in normal use 7 7 /sr0 primary reset input, active low 8 8 v cc power supply 4, 9, nc no connect
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 4 ft8010 ? reset timer with configurable delay time functional description the ft8010 reset timer uses an internal oscillator and a two-stage, 21-bit counter to determine when the output pins switch. time n is set by the hard-wired logic level of the dsr pin. n is either 7.5 20% seconds for dsr=low or 11.25 20% seconds for dsr=high. table 1. ft8010 truth table dsr reset timer ( +-20% ) 0 7.50s 1 11.25s the two input pins, /sr0 and /sr1, drive voltage comparators that compare th e voltage on the input with the voltage set by the reference block. a low input signal on both /sr0 and /sr1 starts the oscillator. the oscillator sends data pulses to the digital core, which includes the counter. there are two scenarios for counting, as described below: short duration and long duration. in the short-durat ion scenario, outputs /rst1 and rst2 are not affected. in the long duration scenario, the outputs change state after time n. the outputs return to their original states when a high input signal occurs on eit her /sr0 or /sr1. the /rst1 output is an open-dr ain driver. when the count time exceeds time n, the /rst1 output drives low. the rst2 output is a push-pull driver. when the count time exceeds time n, the rst2 output drives high. the trig pin should be tied gnd or low during normal operation. the trig pin is a test mode pin used for scan testing. application note important : the dsr pin must be tied to v cc or gnd to provide a high or low voltage level. the voltage level on the dsr pin determines the length of the configurable delay. it is impor tant that the voltage level on the dsr pin not change during normal operation. the dsr pin must be tied directly to v cc or gnd before sr0 or sr1 buttons go low. do not use pull-up or pull- down resistors on the dsr pin. short duration (t w < n) in this case, both input /sr0 and /sr1 are low for a duration t w which is shorter than time n. when an input goes low, the internal timer starts counting. the input goes high before time n. the timer stops counting and resets and no changes occur on the outputs ( see figure 4) . /sr0 /sr1 /rst1 /rst2 description l h l the timer starts counting when bot h inputs go low. the timer stops counting and resets when either input goes high. no changes occur on the outputs, both /sr0 and /sr1 need to be low to activate (start) the timer. l h l figure 4. short duration waveform
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 5 ft8010 ? reset timer with configurable delay time long duration (t w > n) in this case, inputs /sr0 and /sr1 are low for a duration, t w , which is longer than time n. when an input goes low, the internal timer starts counting. after time n, the outputs switch and the timer stops counting. the input goes high sometime after n seconds. when the input goes high, the timer resets and the outputs switch back to their original state after a propagation delay (see figure 5) . /sr0 /sr1 /rst1 rst2 description l the timer starts counting when both inputs go low. after time n, the outputs switch. when either input goes high, the timer resets and the outputs switch back to their original state. both /sr0 and /sr1 need to be low to activate (start) the timer. l figure 5. long duration waveform note: 3. waveforms not drawn to scale (tphl1, tplh1 >> tphl2, tplh2).
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 6 ft8010 ? reset timer with configurable delay time absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter condition min. max. unit v cc supply voltage -0.5 7 v v in dc input voltage /sr0, /sr1, trig, dsr -0.5 7 v v out output voltage (4) /rst1 high or low -0.5 7 v rst2 high or low -0.5 vcc+0.5 /rst1, rst2, v cc =0 -0.5 7 i ik dc input diode current v in < 0 v -50 ma i ok dc output diode current v out < 0 v -50 ma v out > v cc +50 i oh /i ol dc output source/sink current -50 +50 ma i cc dc v cc or ground current per supply pin ? 100 ma t stg storage temperature range -65 +150 ? c t j junction temperature under bias +150 ? c t l junction lead temperature, soldering 10 seconds +260 ? c p d power dissipation 5 mw esd electrostatic discharge capability human body model, jesd22-a114 4 kv charged device model, jesd22-c101 2 note: 4. i o absolute maximum rating must be observed.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 7 ft8010 ? reset timer with configurable delay time recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter condition min. max. unit v cc supply voltage -40c to +85c 1.8 5.0 v -25c to +85c 1.7 5.0 0c to +85c 1.65 5.00 t rfc v cc recovery time after power down v cc =0 v after power down, rising to 0.5 v 5 ms v in input voltage /sr0, /sr1 0 5 v v out output voltage /rst1 high or low 0 5 v rst2 high or low 0 v cc /rst1, rst2, v cc =0 v 0 5 i oh dc output source current rst2, 1.8 v v cc 3.0 v -0.1 ma rst2, 3.0 v v cc 5.0 v -0.5 i ol dc output sink current /rst1, rst2, v cc =1.8 v to 5.0 v +0.5 t a free air operating temperature -40 +85 ? c ? ja thermal resistance mlp-8 245 c/w umlp-10 200 note: 5. all unused inputs must be held at v cc or gnd. dc electrical char acteristics unless otherwise specifie d, conditions of t a =-40 to 80c with v cc =1.8 - 5.0v or t a =-25 to 85c with v cc =1.7 ? 5v or t a =0 to 85c with v cc =1.65 ? 5v produce the performance characteristics below. symbol parameter condition min. max. unit v ih input high voltage /sr0, /sr1 1.2 v dsr 0.65 x v cc v il input low voltage /sr0, /sr1 0.32 v dsr 0.25 x v cc v oh high level output voltage rst2, i oh =-100 a 0.8 x v cc v rst2, i oh =-500 a v cc =3.0 to 5.0 v 0.8 x v cc v ol low level output voltage rst2, i ol =500 a 0.3 v /rst1, i ol =500 a 0.3 i in input leakage current 0 v ? v in ? 5.0 v ? 1.0 a i cc quiescent supply current (timer inactive) /sr0 or /sr1=v cc 20 a dynamic supply current (timer active) /sr0=/sr1=0 v 100
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 8 ft8010 ? reset timer with configurable delay time ac electrical characteristics unless otherwise specifie d, conditions of t a =-40 to 80c with v cc =1.8 - 5.0v or t a =-25 to 85c with v cc =1.7 ? 5v or t a =0 to 85c with v cc =1.65 ? 5v produce the performance characteristics below. symbol parameter conditions min. typ. max. unit t phl1 timer delay, /srn to /rst1, (dsr=0) c l =5 pf, r l =5 k ? see figure 6 6.0 7.5 9.0 s timer delay, /srn to /rst1, (dsr=1) c l =5 pf, r l =5 k ? see figure 6 9.00 11.25 13.50 s t plh2 propagation delay, /srn to /rst1, (dsr=0 or 1) c l =5 pf, r l =5 k ? see figure 6 220 310 ns t plh1 timer delay, /srn to rst2, (dsr=0) c l =5 pf,r l =10 k ? see figure 7 6.0 7.5 9.0 s timer delay, /srn to rst2, (dsr=1) c l =5 pf, r l =10 k ? see figure 7 9.00 11.25 13.50 s t phl2 propagation delay, /srn to rst2,(dsr=0 or 1) c l =5 pf, r l =10 k ? see figure 7 210 300 ns capacitance specifications t a =+25 ? c. symbol parameter conditions typical unit c in input capacitance v cc =gnd 4.0 pf c out output capacitance v cc =5.0 v 5.0 pf
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 9 ft8010 ? reset timer with configurable delay time ac test circuit and waveforms figure 6. /rst1 output
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 10 ft8010 ? reset timer with configurable delay time ac test circuit and waveforms (continued) figure 7. rst2 output
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 11 ft8010 ? reset timer with configurable delay time physical dimensions figure 8. 10-lead, ultrathin mlp, 1.4 x 1.8 x 0.55 mm package package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . a b c seating plane detail a pin#1 ident recommended land pattern notes: a. package does not fully conform to jedec standard. b. dimensions ar e in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. land pattern recommendation is based on fsc design only. e. drawing filena me: mkt-umlp10arev3. top view bottom view 0.15 c 0.08 c 0.15 c 2x 2x side view 0.10 c 0.05 3 6 1 0.10 c a b 0.05 c 0.55 max. 10 1.40 1.80 0.40 0.15 0.25 (10x) 0.35 0.45 (9x) 1.70 2.10 0.40 0.663 0.563 (9x) 0.225 (10x) 1 0.152 0.10 0.10 0.55 0.45 0.10 detail a scale : 2x 1.85 1.45 0.55 0.40 0.225 (10x) 9x 0.45 pin#1 ident optional minimial toe land pattern scale : 2x lead option 1 scale : 2x lead option 2 package edge
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 12 ft8010 ? reset timer with configurable delay time physical dimensions (continued) figure 9. 8-lead, molded leadless package (mlp), 2.0 x 2.0 x 0.8 mm package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . bottom view side view top view notes: a. package conforms to jedec mo-229, variation w2020d except where noted. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. land pattern recommendation based on pcb matrix calculator v2009. e. if center pad is not soldered to, no exposed metal is allowed in the top layer of the board in the area shown. f. drawing filename: mkt-mlp08rrev2. 0.05 0.00 0.80 max 0.10 c 0.08 c (0.20) c seating plane pin1 ident 2.00 2.00 a b 2x 2x 0.10 c 0.10 c 85 14 0.10 cab 0.05 c pin 1 ident 0.50 0.65 0.45 0.25 0.15 8x 8x recommended land pattern (nsmd pad type) option #1: no center pad (0.25) (0.90) 1.80 0.50 8x 8x option #2: with center pad e top layer cu keep out area 0.90 (1.35) a (0.25) (0.90) 1.80 0.50 8x 8x 0.90 (0.35) 1.35 max 0.40 max
? 2009 fairchild semiconductor corporation www.fairchildsemi.com ft8010 ? rev. 1.0.7 13 ft8010 ? reset timer with configurable delay time

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